Used Terms

Most terms described in this section are extracted from the 1076-1993 Standard VHDL Language Reference Manual.

1.

Actual:   An expression, a port, a signal, or a variable associated with a formal port, formal parameter, or formal generic.

2.

Formal:   A formal port or formal generic of a design entity, a block statement, or a formal parameter of a subprogram.

3.

Globally static expression:   An expression that can be evaluated as soon as the design hierarchy in which it appears is elaborated.

4.

Instance name:   A string describing the hierarchical path starting at the root of the design hierarchy and descending to the named entity, including the names of instantiated design entities.

5.

Locally static expression:   An expression that can be evaluated during the analysis of the design unit in which it appears.

6.

Named entity:   An item associated with an identifier, character literal, or operator symbol as the result of an explicit or implicit declaration. Note, named entity and entity declaration are different terms. A entity declaration defines the interface of a component while a named entity denotes any named item (i.e. a variable or constant). To uniquely distinguish both terms a entity declaration will be referred to as ``VHDL entity'' in this document.