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Entity Class Methods

VHDL subprograms defined within an VHDL entity declaration are transformed into member functions of the entity class. Further, each entity class has a constructor and destructor.

Methods Description
'Entity_Class' (name_stack iname,
        map_list *mlist)
Elaborates the declaration part. ``iname'' is the instance name of the current entity, ``mlist'' pointer to a list containing the mapping information for signal and generic parameters of the entity.
~ 'Entity_Class' () A destructor to clean up memory if a component is removed (usually not executed before end of simulation).


ENTITY myentity IS
   PORT (clk : IN BIT; data : INOUT INTEGER);

   FUNCTION SomeFunction RETURN BIT IS ...;
END myentity;
is transformed to
class L7testlib_E8myentity {
  L3std_Q8standard_T7integer         G6genpar;
  signal<L3std_Q8standard_T3bit>     *S3clk;
  signal<L3std_Q8standard_T7integer> *S4data;
  L3std_Q8standard_T3bit F12somefunction() { ... }

  L7testlib_E8myentity(name_stack iname, map_list *mlist);