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Type Info Classes

For each VHDL type a separate type info class is created. From this class a single instance is created. It stores some informations about the type, e.g. lower, left, right and upper bounds. Each type info class is derived from a corresponding base class which actually stores the various informations into variables. On the other hand the derived class provides some special methods to query the same information without accessing the variables of the base class. As the derived classes are unknown to the kernel at kernel compile time it can only read the base class variables. On the other hand code emitted from the code generator uses the special methods provided by the derived class to access the same information faster.