To improve readability of the automatically generated code, a define statement maps each integer type name to a corresponding template instantiation. The type name may now be used to create an VHDL integer instance.
Example:
TYPE myint IS INTEGER 0 TO 1000;is mapped to
#define L3lib_P6mypack_T5myint integer_type<L3lib_P6mypack_I5myint>Note,
L3lib_P6mypack_I5myint is the type info class of the
VHDL integer type myint defined in package mypack of
library lib.