Signals

VHDL processes use signals to communicate with each other. A process may read, write and it may be sensitive on signals. In VHDL there are two kind of signals:

• User defined signals

  User defined signals are explicitly defined in the source code. They may be either a port signal or a signal defined within a concurrent declarative region. Besides the type of a signal additional properties can be associated with a signal:

  • A signal can be associated with a resolution function. This can be dome either explicitly by referring to a corresponding function in the signal declaration or by using a resolved type.
  • Associated with each signal is a direction defining the information flow. Port signals may be associated with a direction IN, OUT, INOUT, BUFFER, or LINKAGE while signals defined within a concurrent declarative region are implicitly associated with the direction INOUT.
  • Signals defined within a concurrent declarative region may be optionally associated with a signal kind REGISTER or BUS.

• Implicit signals

  Implicit defined signals are instantiated by the simulation system. VHDL processes may not assign new values to implicit signals directly, however they may read or may be sensitive on them. Implicit signals fall into two groups:

  • Signal kind attributes are implicitly created by the simulation system for those signals which are prefix of a VHDL attribute DELAYED, TRANSACTION, STABLE, or QUIET.

  • GUARD signals are instantiated by the simulation system for each GUARD expression present in the VHDL source code.

Each (explicit and implicit) signal is represented by an instance of the sig_info<SignalType> template class where SignalType is the actual VHDL data type of the signal (e.g. bit, integer, boolean).