next up previous contents
Next: Processes Up: The FreeHDL Compiler/Simulator System Previous: Architecture Class Instantiation

Concurrent Statements

In VHDL the behaviour of a component can be defined in several ways:

Processes, concurrent signal assignments, and component instantiations may be mixed arbitrarily in order to describe the structure respectively behaviour of a new component.

Note, after elaboration the entire VHDL model consists solely of a set of processes and signals. The processes communicate with each other by reading/writing on these signals respectively shared variables.



 
next up previous contents
Next: Processes Up: The FreeHDL Compiler/Simulator System Previous: Architecture Class Instantiation

1998-11-17