Similar to process code the component instantiation statements are transformed into corresponding C++ statements. However, contrary to processes this statements are executed at elaboration time only. They reside in the constructor code of a corresponding architecture class and indirectly call constructors of the component to be instantiated. Besides executing the constructor of the new component another important task of the instantiation code is to connect the signals of the current component (also called actual signals; see Section 3.1 item 1) with the interface signals (ports) of the new component (also called formal ports/signals; see Section 3.1 item 2). Further it assigns appropriate values to the generic parameters (formal generics/parameters) of the new component.
Beside direct connections between actual and formals (signals or
generic parameters) in VHDL also more complex structures are
supported. E.g. type conversion functions may be used to fit the type
of a formal port signal to an actual signal. Because of these special
features the links between formals and actuals are not directly
established by the instantiation code. Instead, the mapping
information is packed into special mapping info instances of class
map_list which are then passed over to the kernel function
elaborate_component. Based on the mapping information and the
library, entity, and architecture name of the new component this
functions executes the constructor of the corresponding component and
establishes all links between formals and actuals.